1 november 01, 2001 u62h256a 32768 x 8 bit static cmos ram 35 and 55 ns access time common data inputs and data outputs three-state outputs typ. operating supply current 35 ns: 45ma 55 ns: 30ma standby current < 50 a at 125c ttl/cmos-compatible power supply voltage 5 v operating temperature range -40 c to 85 c -40 c to 125 c cecc 90000 quality standard esd protection > 2000 v (mil std 883c m3015.7) latch-up immunity >100 ma package: sop28 (300/330 mil) the u62h256a is a static ram manufactured using a cmos pro- cess technology with the following operating modes: - read - standby - write - data retention the memory array is based on a 6-transistor cell. the circuit is activated by the fal- ling edge of e . the address and control inputs open simultaneously. according to the information of w and g , the data inputs, or outputs, are active. in a read cycle, the data outputs are activated by the falling edge of g , afterwards the data word will be available at the outputs dq0-dq7. after the address change, the data outputs go high-z until the new information is available. the data outputs have no preferred state. the read cycle is finished by the falling edge of w , or by the rising edge of e , respec- tively. data retention is guaranteed down to 2 v. with the exception of e , all inputs consist of nor gates, so that no pull-up/pull-down resistors are required. automotive fast 32k x 8 sram pin configuration top view signal name signal description a0 - a14 address inputs dq0 - dq7 data in/out e chip enable g output enable w write enable vcc power supply voltage vss ground pin description 1 a14 vcc 28 2 a12 w 27 4 a6 a8 25 5 a5 a9 24 3 a7 a13 26 6 a4 a11 23 7 a3 g 22 8 a2 a10 21 12 dq1 dq5 17 9 a1 e 20 10 a0 dq7 19 11 dq0 dq6 18 13 dq2 dq4 16 14 vss dq3 15 sop features description
2 november 01, 2001 u62h256a operating mode e w g dq0 - dq7 standby/not selected h * * high-z internal read l h h high-z read l h l data outputs low-z write l l * data inputs high-z truth table block diagram characteristics a stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specificati on is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability b maximum voltage is 7 v c not more than 1 output should be shorted at the same time. duration of the short circuit should not exceed 30 s. all voltages are referenced to v ss = 0 v (ground). all characteristics are valid in the power supply voltage range and in the operating temperature range specified. dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of v i , as well as input levels of v il = 0 v and v ih = 3 v. the timing reference level of all input and output signals is 1.5 v, with the exception of the t dis -times and t en -times, in which cases transition is measured 200 mv from steady-state voltage. dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v cc v ss w g e row address inputs column address inputs address change detector column decoder row decoder sense amplifier/ write control logic clock generator common data i/o memory cell array 512 rows x 64 x 8 columns a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 * h or l maximum ratings a symbol min. max. unit power supply voltage v cc -0.5 7 v input voltage v i -0.5 v cc + 0.5 b v output voltage v o -0.5 v cc + 0.5 b v power dissipation p d -1w operating temperature k-type a-type t a -40 -40 85 125 c storage temperature t stg -65 150 c output short-circuit current at v cc = 5 v and v o = 0 v c | i os | 200 ma
3 november 01, 2001 u62h256a d -2 v at pulse width 30 ns recommended operating conditions symbol conditions min. max. unit power supply voltage v cc 4.5 5.5 v input low voltage d v il -0.3 0.8 v input high voltage v ih 2.2 v cc + 0.3 v electrical characteristics symbol conditions min. max. unit supply current - operating mode supply current - standby mode (cmos level) supply current - standby mode (ttl level) i cc(op) i cc(sb) i cc(sb)1 v cc v il v ih t cw t cw v cc v e v cc v e k-type a-type = 5.5 v = 0.8 v =2.2 v = 35 ns = 55 ns =5.5 v = v cc - 0.2 v = 5.5 v = 2.2 v 90 70 50 10 20 ma ma a ma ma output high voltage output low voltage v oh v ol v cc i oh v cc i ol = 4.5 v = -4.0 ma =4.5 v =8.0 ma 2.4 0.4 v v input high leakage current input low leakage current i ih i il v cc v ih v cc v il = 5.5 v = 5.5 v = 5.5 v = 0 v -2 2a a output high current output low current i oh i ol v cc v oh v cc v ol =4.5 v =2.4 v =4.5 v =0.4 v 8 -4 ma ma output leakage current high at three-state outputs low at three-state outputs i ohz i olz v cc v oh v cc v ol =5.5 v =5.5 v =5.5 v =0 v -2 2a a
4 november 01, 2001 u62h256a switching characteristics read cycle symbol 35 55 unit alt. iec min. max. min. max. read cycle time t rc t cr 35 55 ns address access time to data valid t aa t a(a) 35 55 ns chip enable access time to data valid t ace t a(e) 35 55 ns g low to data valid t oe t a(g) 15 25 ns e high to output in high-z t hzce t dis(e) 15 20 ns g high to output in high-z t hzoe t dis(g) 12 15 ns e low to output in low-z t lzce t en(e) 33ns g low to output in low-z t lzoe t en(g) 00ns output hold time from address change t oh t v(a) 33ns e low to power-up time t pu 00ns e high to power-down time t pd 35 55 ns switching characteristics write cycle symbol 35 55 unit alt. iec min. max. min. max. write cycle time t wc t cw 35 55 ns write pulse width t wp t w(w) 20 35 ns write setup time t wp t su(w) 20 35 ns address setup time t as t su(a) 00ns address valid to end of write t aw t su(a-wh) 25 40 ns chip enable setup time t cw t su(e) 25 40 ns pulse width chip enable to end of write t cw t w(e) 25 40 ns data setup time t ds t su(d) 15 25 ns data hold time t dh t h(d) 00ns address hold from end of write t ah t h(a) 00ns w low to output in high-z t hzwe t dis(w) 15 20 ns g high to output in high-z t hzoe t dis(g) 12 15 ns w high to output in low-z t lzwe t en(w) 00ns g low to output in low-z t lzoe t en(g) 00ns
5 november 01, 2001 u62h256a e - controlled data retention 4.5 v t su(dr) t rec v cc e v cc(dr) 2 v 0 v 2.2 v 2.2 v v cc(dr) - 0.2 v v e (dr) v cc(dr) + 0.3 v data retention characteristics symbol conditions min. typ. max. unit alt. iec data retention supply voltage v cc(dr) 25.5v data retention supply current i cc(dr) v cc(dr) = 3 v v e = v cc(dr) - 0.2 v 30 a data retention setup time t cdr t su(dr) see data retention waveforms (above) 0ns operating recovery time t r t rec t cr ns test configuration for functional check dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v ih v il v ss v cc 5 v 481 255 30 pf e v o input level according to the relevant test measurement simultaneous measure- ment of all 8 output pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 e w g e in measurement of t dis(e) ,t dis(w) , t en(e) , t en(w) , t en(g) the capacitance is 5 pf. data retention mode
6 november 01, 2001 u62h256a capacitance conditions symbol min. max. unit input capacitance v cc v i f t a = 5.0 v = v ss = 1 mhz = 25 c c i 7pf output capacitance c o 7pf all pins not under test must be connected with ground by capacitors. ic code numbers u62h256a s a 35 type package s = sop28 300 mil s1 = sop28 330 mil operating temperature range k = -40 to 85 c a = -40 to 125 c access time 35 = 35 ns 55 = 55 ns the date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week.
7 november 01, 2001 u62h256a t pu t dis(g) t dis(e) t cr previous data valid output data valid address valid address valid t su(a) high-z t en(e) t en(g) t a(g) t a(e) read cycle 1: a i -controlled (during read cycle : e = g = v il , w = v ih ) read cycle 2: g -, e -controlled (during read cycle: w = v ih ) t a(a) t cr t v(a) a i dq i output a i g dq i output t pd i cc(op) i cc(sb) 50 % 50 % output data valid e
8 november 01, 2001 u62h256a write cycle1: w -controlled t h(d) a i e w dq i input g dq i output t cw t su(e) t h(a) t w(w) t su(a) t su(d) t dis(w) t en(w) address valid input data valid high-z t su(a-wh) write cycle 2: e -controlled input data valid t su(a) t h(d) a i e w dq i input g dq i output t cw t w(e) t h(a) t su(w) t su(d) t dis(w) t e n ( e ) high-z address valid t dis(g) l- to h-level undefined h- to l-level the information describes the type of component and shall not be considered as assured characteristics.terms of delivery and rights to change design reserved.
zentrum mikroelektronik dresden ag grenzstra?e 28 ? d-01109 dresden ? p. o. b. 80 01 34 ? d-01101 dresden ? germany phone: +49 351 8822 306 ? fax: +49 351 8822 337 ? email: sales@zmd.de ? http://www.zmd.de november 01, 2001 u62h256a life support policy zmd products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the zmd product could create a situation where personal injury or death may occur. components used in life-support devices or systems must be expressly authorized by zmd for such purpose. limited warranty the information in this document has been carefully checked and is believed to be reliable. however zentrum mikroelektronik dresden ag (zmd) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. the information in this document describes the type of component and shall not be considered as assured charac- teristics. zmd does not guarantee that the use of any information contained herein will not infringe upon the patent, trade- mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. this document does not in any way extent zmd?s warranty on any product beyond that set forth in its standard terms and conditions of sale. zmd reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
change record date name change 31.01.2001 steffen buschbeck initial release of u62h256a based on u62h256s 29.08.2001 steffen buschbeck wilfried hofrichter shortened description (page 1) adjusted block diagram to array organization (page 2) changed address valid to end of write 20 -> 25 (page 4)
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